Diploma thesis
Readout chain for high-resolution hadronic calorimeters with silicon photomultipliers
Johannes Gutenberg University Mainz, ATLAS Group / CALICE / ILC
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- Date
- 2013-07-15
This page is his own thesis. The sections below describe what the work covers, how it was built, and the part he delivered.
What it covers
This is the diploma thesis of Dr. Andree Welker: the readout chain for a highly granular hadron calorimeter with silicon photomultipliers, done in the Mainz ATLAS group for CALICE / ILC. The board itself was one metre long, twelve layers, with four FPGAs. It is a one-year, end-to-end detector delivery, not a literature review.
The path into that year was already built: Delphi apprenticeship electronics, PCB design, programming, metalworking, house wiring, and Siemens S7, then university minors in electronics, computer science, nuclear chemistry, and mathematics. The diploma is where that stack became this one-metre calorimeter board.
Methods and setup
He designed and programmed a one-metre, twelve-layer printed circuit board with four FPGAs and a Zynq Mars board as Link Data Aggregator. He populated the board, sent manufacture out for speed, wrote the firmware, took the chain to first beamtime, and analysed the data. Resources, effort, cost and time were planned across hardware and software together.
The architectural cut: thousands of data cables became one Ethernet link, so dead material could leave the detector. A highly granular CALICE calorimeter needs that aggregator if the channels are to leave the hall as data rather than as a cable harness.
Why it matters
A future lepton-collider calorimeter only works if the readout can leave the hall as data, not as a harness. The one-metre, twelve-layer board with four FPGAs is that step: the Link Data Aggregator that made a scalable CALICE-style system usable in beam.
It is also why the nuclear-physics doctorate was a direct next step rather than a restart. The same person who could design, program, and commission a one-metre, twelve-layer FPGA board could later implement PI-ICR electronics and software on a Penning trap. A public thesis file is not yet linked; this delivered board is the record.
His part
This page is the diploma thesis of Dr. Andree Welker. Other papers in this archive list him among many authors.
He designed the one-metre, twelve-layer board with four FPGAs, programmed the firmware, took it to beam, and analysed the data. The ILC TDR and the CALICE notes in this archive are community papers. This year is that metre-long Link Data Aggregator, the board that turns a highly granular calorimeter into a data system.